In general, semiconductor devices include a device isolation area for electrically separating respective circuit patterns and a device formation area for forming respective circuit patterns.
According to the recent high integration of semiconductor devices, methods for reducing a device isolation area and a device formation area are being suggested.
The most common method for forming the device isolation area is STI (Shallow Trench Isolation).
Hereinafter, a method for forming an isolation layer in a semiconductor device according to the related art will be described with reference to the accompanying drawings.
FIGS. 1a through FIG. 1d are cross-sectional views for illustrating a method for forming an isolation layer in accordance with the related art.
Referring to FIG. 1a, an oxide layer 102 and a nitride layer 103 are deposited on a semiconductor substrate 101.
A photosensitive resist is coated on a top surface of the nitride layer 103 and patterned by an exposure and developing process to form a photoresist layer pattern 104 exposing the nitride layer 103 on an isolation region.
Referring to FIG. 1b, a trench 105 having a predetermined depth is formed by performing an etching process using the photoresist layer pattern 104.
The photoresist layer pattern 104 is removed through a cleaning process, and a thermal oxidation layer 106 is formed in the trench 105 by a thermal oxidation process.
Then an isolation bed 107a is formed by performing a gap fill (isolation material) process on the substrate including the thermal oxidation layer 106 in the trench 105.
Material used for forming the isolation layer 107a is a high density plasma oxide.
Referring to FIG. 1c, a planarization process is performed on the surface of the semiconductor substrate 101 until the nitride layer 103 is exposed to form the isolation layer 107 from the isolation bed 107a. 
Herein, the semiconductor substrate 101 is planarized through CMP (Chemical Mechanical Polishing) process, and the isolation layer 107 is formed inside of the trench 105.
Referring to FIG. 1d, the oxide layer 102 and the nitride layer 103 are removed by a wet etching and cleaning process.
Accordingly, a device isolation layer is formed in the device isolation area by the isolation material filled in the trench 105.
However, as semiconductors become smaller and highly integrated, the isolation layers become deeper and more narrow.
Therefore, it becomes more and more difficult to completely fill isolation material in a trench that is formed deep and narrow due to the increasingly high level of integration of devices.
Accordingly, the conventional chemical deposition method may not be capable of securing the gap fill margin of isolation material filled in a deep and narrow trench.